basalt

An NVIDIA GPU instruction is 128 bits, and 21 of them are not the instruction at all. They are a scheduling control word: how many cycles to stall, which scoreboards to signal, which to wait on. The hardware does not check any of it. On sm_120 there is no interlock on fixed-latency instructions, so if a stall count is shorter than the latency of a value the next instruction reads, nothing faults and nothing warns. It computes on stale data, at full speed, every single time. That is a bug that does not crash and does not show up in a debugger. It just returns numbers that are quietly wrong.

Compilers and assemblers write those bits. Nothing read them back and said whether they were safe. Building the thing that does meant deriving the instruction set by experiment rather than documentation: take an encoding that assembled, flip one bit, decode the result, record what moved.

The hard part is that a checker calibrated on a corpus cannot fail on that corpus. The tightest gap the compiler was seen to leave becomes the floor, by construction. So the real test was machine code basalt had never touched: NVIDIA's own shipped libraries, held out of every table the checker reads. The first run reported 6,593 errors in a JPEG decoder that has never returned a wrong pixel, and not one of them was NVIDIA's. Thirteen were defects in basalt's own model, each invisible on a corpus it generates itself. Fixing those took it to zero, and zero over one library was not evidence either, so widening the held-out set by a factor of eighty took it straight back to 940 and found five more. All thirteen corrections are written up.

Two more tools exist to keep that one honest. The assembler has to reproduce the vendor compiler's exact 128 bits, and does so for 4,585,336 of 5,237,448 shipped instructions with zero wrong, refusing anything it cannot place by name rather than guessing. The scheduler throws away every control bit the compiler chose, computes its own, and the GPU computes byte-identical results for 439 of 439 comparable kernels. A checker and a scheduler sharing a latency model will agree with each other while both being wrong, so only the silicon settles it.

Nothing NVIDIA wrote is in it. No source, no headers, no documentation: it drives their publicly distributed binaries as external processes and records what they do, which is the footing this kind of work has stood on for over a decade. The release is archived with a DOI, so a number quoted from it points at a fixed commit rather than at a moving branch.